ASIC Design Engineers - DFT expertise (San Jose)

  • Address:San Jose, CA 95110 (map)
  • Date Posted:08/25/16
  • Job Type:Full-time
  • Description:
  • eSilicon is seeking highly experienced DFT Engineering Specialists with strong background in all DFT and IP test development disciplines in the design phase and support for test bring up in the ATE environment.The successful candidates will assist on active ASIC projects in DFT and IP test development and will also be key consulting resources to support our global DFT team and Test and Operations team. These experienced engineers will become part of a growing eSilicon core DFT expert team in support of an increasing number of active ASIC projects.Responsibilities include:Be the subject matter expert for all relevant DFT disciplines for complex FinFET class of networking chips. The person can be the DFT lead for these projects or can also provide DFT consultation for all projects.Hands on development or consultation for EDA-tool driven scan, scan compression, memory BIST/ repair, ATPG, hierarchical scan and boundary scan.Sign-off timing constraint development for DFT and test modesSign-off Simulation, STA, and formal verification for DFT and test modesAutomated debug using scan tester datalogs, or TAP-based debug softwareAutomated MBIST/repair debugTroubleshooting any No Trouble Found (NTF) device RMA’s.IP test vector development and debug experience for DDR/SerDes loopback, DLL/PLL, and other hard IP cores such as HBM2 PHYSupport eSilicon’s Test Engineering team for structured DFT and IP test bring-up with a quick ramp to characterization and volume production.Serve as a prime consultant to assist with any unexpected test bring-up issues.Optimize test time while maintaining high coverageRequired Background and Skills include:Candidates must possess an outstanding grasp across all aspects of DFT methods and implementation with a minimum of 10 years relevant DFT experience requiredConsidered by peers an expert in EDA DFT flows, especially using Mentor/Synopsys test tools for boundary scan, memory bist and test compression scan and hierarchical scan and have the experience in using these flows on complex chipsCandidates must possess strong background in hard IP such as Serdes and DDR test development and debugFamiliarity with interposer, 2 1.2D and HBM2 class of designs is a big plusCandidates must possess strong background in supporting test bring-up and debug of DFT and IP testsStrong background in logic design and verification in related areas in a big plusStrong background in test programs and testers is a big plusSkilled with TCL and shell scriptingDemonstrated ability to innovate, take the next logical step, and solve complex technical issues based on the symptoms at hand, especially in pre tapeout DFT simulation or post tapeout test bring-up debuggingCollaborative personality to work as part of a team, consult and advise, and interacting with customersBS/MS in EE/CE, or equivalentExperience working with customers and colleagues in Asia a big plusEnglish fluency is required, Vietnamese and Mandarin Chinese is a plusMust be eligible to work in country of hire without restrictionsNo relo assistance available at this timeOnly those candidates who meet the requirements listed herein will be given consideration.eSilicon has design centers worldwide San Jose, CA Allentown, PA, Barcelona, SP Bucharest, RO Shanghai, CH and is open to staff these positions with experienced Engineers located in these cities - immediate openings (no relocation assistance available at this time). 
Ad ID: 45745768
  • Posted by: Ad Partner | View all ads
  • Profile: Active since 08/2016
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